Subject: Read This
Date: 12/23/2004 11:09:40 AM (GMT-7)
IP Address: 126.96.36.199
In Reply to: This is PCI-X posted by
>Even though PCI Express is only now making its way into the marketplace, the specification's overseeing body is already describing the next generation of the technology, which will see its transfer rate doubled.
The PCI Special Interest Group said today that PCI Express 2.0 will feature a transfer rate of 5.0 gigatransfers per second.
While it might seem like an early move to the uninitiated, SIG chairman Tony Pierce said the group's decision helps pave the way for a typical industry spec cycle that won't be put into practice for years.
Indeed, he said, PC and board manufacturers have been eager to get started on exploring ways to move up from the current 2.5 gigatransfers per second.
"A lot of our members have been asking for it -- 'What are the design points for our systems 3 years from now?'" he said. "They need to start thinking about load balancing and system design ... this puts us on a specification for actually how to build that."
Getting the decision made on data rate clears one hurdle toward agreement on the PCI-E 2.0 spec, and toward building devices that use the design.
"This was what we thought was the best point the industry could build and rally around," said Piece, who also serves as head of Microsoft's PCI and ACPI efforts. "It's more or less for all the teams looking at system designs and putting everyone on a roadmap so they know what the design is. And it affects design architecture within system and devices, and all the areas in which PCI Express is becoming dominant."
The group based its decision to standardize on 5 gigatransfers per second to minimize engineering and manufacturing hurdles -- and to help in backwards compatibility.
"We actually examined several data rates ranging from 5 [gigatransfers per second] all the way up to 6.25 gigatransfers ... and some of the other data rates being used in other areas of the industry," Pierce said. "The decision came down to a defined set of parameters we have for our interconnect -- when you move to generation two of anything, it has to be backwards compatible."
"It's got to be done in high-[volume] manufacturing, and our usage of the exact connector that's being deployed today is of the utmost importance to us," he added. "When we examined all the parameters, we had to design around and be looking at channel characteristics and systems we had to support ... The general conclusion was while faster was always better, with 5 gigatransfers, this is something everyone can build."
Related to its backwards compatibility, the 2.0 spec also will roll in power-management features controlled through software -- which will be necessary as bus power requirements climb.
"The 'gen-two' spec ... will also have some software-controlled parameters put in to allow even a 5 gigatransfer card to run at 2.5" gigatransfers, Pierce said. "That's the deal with some of your power-optimized cases. A perfect example of this is a PCI Express graphics device on a laptop computer -- When you're plugged in to the wall, you may just want it to run all-out. But if you're on an airplane, you want to get through that DVD [using less power]. That will be in the next spec."
He added that in the meantime, PCI Express 1.0 implementations are likely to begin offering increased power management capabilities -- and decreased power consumption.
"There's a lot more elegant features in the base [1.0] spec released a year ago that aren't being delivered yet -- they aren't priority one," Pierce said. "There's a lot of things on power management. You're going to see more and more deployment of these features and devices as we move to the second-generation parts."
But Pierced warned that a good deal of effort will still be required before 2.0, with its software-controlled power management, becomes a viable specification.
"By no means is 5 gigatransfers going to be easy -- it's going to take some very, very good engineering to make this work at all," he said.