This Article was last modified in November, 1998.
- Performance-optimized AMD-K7 chipsets are planned from both AMD and leading third-party vendors in 1999
- High quality, performance-optimized AMD-K7 motherboards are planned from leading vendors at launch in 1H99
- Production BIOS are planned from all leading suppliers including AMI, Award and Phoenix
- The AMD-K7 processor will utilize existing industry-standard physical/mechanical infrastructure components including cases, power supplies, fans, heat sinks, etc.
AMD had a chance to show off it's new K7 processor at this years Comdex, and what was shown was a truly impressive processor, which will definitely help AMD to compete with Intel's future Katmai processors and beyond. The following preview is a bit of information I have collected on the K7 after talking to one of AMD's PR reps.
AMD has decided to ditch the aging Socket-7 layout with it's K7, and instead will use a "Slot" interface to connect to the motherboard. The K7 will be housed on a CPU module, just like current Pentium II processors, with the L2 cache present on the same PCB. And like the Pentium II, AMD will use plastic casings to cover the board. Initially, the K7 will contain 128 kilobytes of Level 1 (twice as much as the K6-2), and 512 KB to 1MB of L2 cache. AMD also claims that the K7 will possess an advanced floating-point unit which, with the help of 3DNow!, will help to further enhance 3-D and multimedia processing. This advanced FP unit will supposedly help the K7 out-perform other x86 processors by 2x when it hits the market. AMD feels that their advanced FPU, along with their 3DNow! technology, will be strong enough to compete with Intel's upcoming KNI instruction set.
Although the Slot interface used with the K7 (called "Slot A") will be mechanically interchangeable with Intel's Slot 1 interface, the two parts will not electronically compatible, and motherboards designed for AMD's K7 will not be able to take Intel CPUs (and vice-versa). AMD claims that by using this design, manufacturers can use parts already available on the market to build K7 motherboards. The K7 will also be AMD's first SMP-capable desktop CPU - meaning that people will be able to have dual, and maybe even quad, K7 systems.
Unless K7 motherboards have the option to run the memory bus asynchronously (at 100MHz), new types of RAM, such as DDR SDRAM or RDRAM will need to be used in order to accommodate the high speed 200MHz bus which will be used on EV6 compatible boards.
AMD's K7 uses a 200MHz bus technology which was originally designed for the high-end Alpha processor, called the "EV-6". At Comdex, AMD demonstrated a new motherboard that has a very similar design to current ATX Slot 1 motherboards. Interestingly, the motherboard appears to be using a chip set designed by AMD itself. At the show however, AMD also announced that Acer and Via Systems will produce chips sets that will work with the K7.
AMD claims that the K7 is being engineered on-schedule, and the will be able to deliver the K7 in the first half of next year at clock speeds starting at 500MHz. The K7 will initially make it's debut around early August or late July at .25 micron, and then (hopefully with no delays), move into a .18 micron process around October or November.
How much will it cost? At the moment, no one is absolutely sure. However, since the K7 will probably be able to outperform Intel's extremely expensive Xeon processor, the K7 definitely won't be too cheap. AMD could unfortunately not quote me a price, however, speculative prices are floating on the net that are between $700 and $900, depending on the L2 cache options you choose.
|AMD-K7 Processor Overview ||AMD-K7 Features:|
- Superior 7th Generation CPU Design
- Leading Performance in Integer, Floating point, and Multimedia
- Operating Frequencies of 500 MHz+ using 0.25mm Technology
- High-speed Alpha(TM) EV6 Bus Technology
- High-speed Backside Level 2 Cache Controller
- Scalable Multiprocessing Architecture for Workstation and Server Markets
- Processor Module for Standard Motherboard Form Factors
- Optimized Chipsets, Motherboards and BIOS
- Nine-issue Superscalar Microarchitecture optimized for high clock frequency
- Superscalar Pipelined Floating Point Unit
- 128KB of on-chip level one (L1) cache
- Programmable High-Performance Backside L2 Cache Interface
- 200 MHz Alpha EV6-Compatible System Bus Interface
- Support for Scalable Multiprocessing
|AMD-K7 Processor Architecture|
- Three Parallel x86 Instruction Decoders
- 9-issue Superscalar Microarchitecture Optimized for High Frequency
- Dynamic Scheduling with Speculative, Out-of-Order Execution
- 2048-entry Branch Prediction Table & 12-entry Return Stack
- 3 Superscalar, Out-of-Order Integer Pipelines each Containing:
- Integer Execution Unit
- Address Generation Unit
- 3 Superscalar, Out-of-Order Multimedia Pipelines with 1-cycle throughput
- FADD (4 cyc latency), MMX ALU (2 cyc latency), 3DNow!
- FMUL (4 cyc latency), MMX ALU (includes Mul & MAC), 3DNow!
- Level 1 64K I-Cache & 64K D-Cache, each 2-way Set Associative
- Multi-level TLB (24/256-Entry I, 32/256-Entry D)
- Two General Purpose 64-bit Load/Store Ports into D-Cache
- 3-Cycle Load Latency
- Multi-banking Allows Concurrent Access by 2 Load/Stores
- High-speed 64-bit Backside L2 Cache Controller
- Supports Sizes of 512KB to 8MB
- Programmable Interface Speeds
- High-speed 64-bit System Interface
- First Mainstream Systems to have a 200MHz Bus
- Significant Headroom for Future
- Deep Internal Buffering to Support Pipelines and External Interfaces
- Up to 72 x86 instructions in-flight
- 32 outstanding load misses
- 15-entry integer scheduler
- 36-entry floating point schedule