the most interesting part
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Subject: the most interesting part
Date: 11/16/2001 7:07:46 PM (GMT-7)
IP Address: 220.127.116.11
In Reply to: nice article posted by
was left out of the picture. Hammer not only integrates the memory controller on the CPU which saves over 50 % access latencies but also is the first design with fully shared caches. This means that in case of an invalid cache, the CPU needs not to go back to the main memory to get the valid data/instructions but can access them from the valid cache of the CPU whodunnit the last time.
This is not of any interest for single CPU platforms but for 2, 4 or 8 way solutions and further basis for AMD's claims that they won't need any large L3 cache....
It'll be interesting to see what comes out of this.
On the other side of the spectrum, Intel is still ramping up clock speed and new transistor technology which goes down to the atomic level and the i845D chipset that might be faster than the SIS pendant. Only time will tell but Northwood with its 512 kB L2 does look interesting. Interesting enough to write a review on it once time is ripe...
On a side note, VIA is releasing its P4X266A chipset next week which will have similar enhancements as the KT266A over the present design so expect a screamer there.
Then there is the new SIS 745 chipset with asynchronous memory bus running at 166 / 200 MHz and everyone including AMD and me is curious whether this will boost performance comparable to the increase in fsb...
Not to forget the other side of the chipset war: nVidia against ATi3...
this was as condensed as I could get a Comdex coverage without breaking NDAs.... (hehe)
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