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Subject: Re: Follow-up questions for MS on RAM and Win98.
Name:
MS
Date: 11/11/2001 8:53:38 AM (GMT-7)
IP Address: 66.1.98.99
In Reply to: Follow-up questions for MS on RAM and Win98. posted by
Dunedain
Message:
There is basically no cacheable area limitation with any of the newer boards. That is, only with the VX / TX chipsets as well as most other socket 7 boards that were using on-board L2 caches was there such a thing, depending on the width of the tagRAM used. For example, VX, TX chipset: 64 MB,
ALi Aladdin5: 128/256 MB depending on the chips used (the internal tagRAM of the chipset was broken so they needed to add extra on the mainboard using 8 or 10 bit chips) VIA VP2, MVP2, MVP3, MVP4: 128-512 MB, depending on write-through or write-back protocol used and chip configuration.
The PII put the L2 on the chip (backboard) and increased the cacheable area to 4 GB, with the newer CPUs it is even higher but I don't know how much each chip can go (up to 64 GB I believe).
In other words, there is no reason to worry about exceeding the cacheable area because the OS puts a much lower cut off. (Win9x: 820 MB, NT:2GB, Win2K4 GB)
Never had any problem with 768 MB under Win98, was a little bit worried when I did the P4 roundup and had to stick 768 MB into the 850 chipset board (couldn't find c-RIMMs) but it ran like a charm.
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