Date: 8/26/2001 10:37:37 PM (GMT-7)
IP Address: 126.96.36.199
In Reply to: Registerd DIMMS... posted by Celstk855
in order to reduce the load on the memory clock, you add a PLL and in order to generate more addresses, you add the register chip. Because the register chip needs one clock cycle to translate the address and data, you have one additional initial latency cycle on every bank activate.
|[ View FollowUps | Post Followup | Main ]|
[No follow-ups for this posting]
Post a Followup