Re: Registerd DIMMS...

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Subject: Re: Registerd DIMMS...
Name: MS
Date: 8/26/2001 10:37:37 PM (GMT-7)
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In Reply to: Registerd DIMMS... posted by Celstk855

in order to reduce the load on the memory clock, you add a PLL and in order to generate more addresses, you add the register chip. Because the register chip needs one clock cycle to translate the address and data, you have one additional initial latency cycle on every bank activate.

ECC stands for data integrity verification which was later changed into error check and correction which really misses the point.

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