Re: Memory

it is quite easy: Eache chip has certain timing characteristics as e.g bank cycle time, RAS to CAs delay and CAS latency. There are about 70 such parameters that are given in ns, e.g. a good part nowadays has a typical CAS latency of around 12-13 ns.

When the SPD is programmed, these parameters are put in, usually according to the chip manufacturer's specifications since most 3rd party vendors don't speck the chips individually.

Very often, there is a 20-30 safety margin on these timings, often, it is even more, as the die gets cleaner, the chips get faster, the specks, however, stay the same (characterization is not too painful but you need some equipment for that).

If you have a spec of let's say 16 ns, that would make the DIMM a CAS-2 at 100 MHz (2 x 10 ns > 16 ns) but CAS 3 at 133 (2 x 7.5 ns < 16 ns and you can only use full clock cycles, of course).

This doesn't mean that the DIMM won't run at 133 MHz CAS-2 because the chips may be better than the specs.

In addition, the JEDEC specifications of PC133 call for CAS-3, so there is another possibility that the proggie just uses these JEDEC guidelines and says:
"it's good enough for PC100 CAS2 and will run at 133 MHz (but there is only a CAS-3 spec so it has to be that ... )"