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Cayenne



This Article was last modified in March, 1998.

The Cyrix Cayenne is Cyrix's next-generation 6x86MX processor core. CPUs based on the Cayenne core may be the first ever to leapfrog over Intel's processors, in terms of speed and performance. The weak FPU that plagued the original 6x86 and 6x86MX will completely disappear in this new core, and these processors should be able to easily match Intel's Pentium II in any 3D application.

The Cayenne will feature a fully pipelined, dual-issue floating point unit and 15 new multimedia floating point instructions to enable the highest-performance 3D graphics, DVD and 3D audio.

"Future applications will require a no-compromise compute engine with balanced integer, floating point and multimedia capability," said Robert Maher, vice president of engineering, Cyrix. "The Cayenne core will deliver industry-leading 3D and multimedia performance for mainstream desktop PCs."

Boost in Floating Point and MMX Instruction Performance
A key component of the Cayenne core is the ability to execute four floating point operations per cycle using dual MMX instruction units. This will deliver over 1 GFLOP peak performance, a first for desktop PCs. In addition, the dual floating point reciprocal and reciprocal-square-root instructions will execute five times faster on Cayenne than on the Pentium II processor. These instructions are used extensively in lighting calculations for 3D image processing.

The net result is that Cayenne will deliver in excess of 10 million meshed triangles per second to an external 3D rendering engine – more than five times faster than the Pentium II processor. Lastly, Cayenne will deliver single-cycle throughput on standard x86 floating point instructions.

Cayenne Core Summary
The Cayenne core will feature a dual-issue floating point and MMX instruction unit, 64KByte L1 cache, and an enhanced sixth-generation integer unit. Processors based on the core will initially be manufactured using a .25-micron, 5-layer metal process. This includes a C4 process for flip chip assembly. As a result, the core die size is expected to be about 65mm2. Processors based on this core are expected to be in production in 2H98 at speed ratings ranging from PR300 to PR400.

About Cyrix
All of the information found above and more can be found at Cyrix's website:
www.cyrix.com

The Cayenne is still under heavy development, and I will keep you posted as this chip progresses.


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